|
|
e71d7388d7
|
Added buffers to outputs and scaling to cv inputs
|
2023-07-06 22:33:18 +03:00 |
|
|
|
da9a38274c
|
Draft pcb layout
|
2023-07-06 12:31:11 +03:00 |
|
|
|
4d715b4e5d
|
fixed polarity and encoder pins in the schematics
|
2023-07-06 01:21:28 +03:00 |
|
|
|
7edd4eae85
|
REV 1
|
2023-03-16 00:59:41 +02:00 |
|
|
|
2d4f39125d
|
added panel
|
2023-02-13 03:31:38 +02:00 |
|
|
|
5fd754a275
|
updated pcb
|
2023-02-12 22:00:08 +02:00 |
|
|
|
6cc7bccc9e
|
added random chance, some progress on pcb
|
2023-02-12 00:58:04 +02:00 |
|
|
|
6b190610f2
|
fixing broken branching (I guess)
|
2023-02-10 01:27:09 +02:00 |
|
|
|
ef82663e6f
|
Updated values in schematics and assigned footprints
|
2023-02-09 23:23:59 +02:00 |
|
|
|
ce6643453e
|
added interrupt for external clock
|
2023-02-07 23:18:30 +02:00 |
|
|
|
85800d7217
|
Added pulldown resistor for analogue inputs
|
2023-02-04 12:48:38 +02:00 |
|
|
|
e4b3c79450
|
Updated schematics
|
2023-02-02 01:03:05 +02:00 |
|
|
|
239d95d272
|
Updated schematics
|
2023-02-02 00:50:43 +02:00 |
|
|
|
4f6e5c8d69
|
schematics partly done
|
2023-02-01 14:04:46 +02:00 |
|
